1. Field of the Invention
The present invention is related to multichip modules (MCMs). More specifically, the present invention provides MCM substrates, as well as to a method for making multichip module substrates and to a method for deplating defective capacitors.
2. Description of the Prior Art
Multilayer circuit structures can be used to electrically communicate two or more electrical devices such as two or more computer chips. Multilayer circuit structures typically contain multiple conductive layers separated by one or more dielectric layers. Via structures disposed in apertures in the dielectric layers provide conductive paths so that electrical signals can pass from one conductive layer to another conductive layer. Multiple via structures in successive dielectric layers can be used to form a conductive path from an inner region to an outer region of a multilayer circuit structure.
Multichip module (MCM) packages require off-module connections to receive input signal, to provide output signals, and to receive power and ground voltages. In low-cost, low performance MCM modules, these off-module connections are usually around the periphery edges of the MCM's substrate. In higher-cost, higher performance MCM modules, the off-module connections are formed through the MCM's substrate which usually comprises a multilayer ceramic material.
Discrete surface-mount or chip capacitors are often added to the surface of a MCM substrate to remove (e.g., de-couple) noise between the power lines and the ground lines. However, as the operating frequency of MCMs has increased, the effectiveness of these surface mount and chip capacitors has decreased to marginal and unacceptable levels.
The via structures in successive dielectric layers can be staggered in a multilayer circuit structure. For example, as shown in FIG. 37, a plurality of staggered via structures 110 are in electrical communication with each other. The staggered conductive path formed by the via structures 110 can provide communication between a core structure 120 and an outer surface of the multilayer circuit structure 100. Each of the via structures 110 shown in FIG. 37 is in the form of a conductive coating on an aperture wall in a dielectric layer. Unfortunately, staggering the via structures can consume valuable area in a multilayer circuit structure and can increase the signal run length. This can decrease the density of the circuitry in a multilayer circuit structure. Moreover, the metal coating of via structures of the type shown in FIG. 37 is thin. Open circuits can form if the coating is not thick enough or is not uniform.
A patentability investigation was conducted and the following U.S. Patents were discovered: U.S. Pat. No. 3,867,272 to Rust et al.; U.S. Pat. No. 4,729,970 to Nath et al.; U.S. Pat. No. 4,749,454 to Arya et al.; U.S. Pat. No. 4,782,028 to Farrier et al.; U.S. Pat. No. 4,984,358 to Nelson; U.S. Pat. No. 5,202,018 to Horántl et al.; U.S. Pat. No. 5,543,585 to Booth et al.; U.S. Pat. No. 5,591,678 to Bendik et al.; U.S. Pat. No. 5,656,548 to Zavracky et al.; U.S. Pat. No. 5,656,552 to Hudak et al.; U.S. Pat. No. 5,716,881 to Liang et al.; U.S. Pat. No. 5,770,487 to Maas et al.; U.S. Pat. No. 5,784,261 to Pedder; U.S. Pat. No. 5,807,783 to Gaul et al.; U.S. Pat. No. 5,811,879 to Akram; U.S. Pat. No. 5,838,545 to Clocher et al.; U.S. Pat. No. 5,843,806 to Tsai; U.S. Pat. No. 5,851,845 to Wood et al.; U.S. Pat. No. 5,856,937 to Chu et al.; U.S. Pat. No. 5,859,397 to Ichinose et al.; U.S. Pat. No. 5,863,412 to Ichinose et al.; U.S. Pat. No. 5,863,829 to Nakayoshi et al.; U.S. Pat. No. 5,866,441 to Pace; U.S. Pat. No. 5,872,025 to Cronin et al.; U.S. Pat. No. 5,872,700 to Collander; and U.S. Pat. No. 5,877,034 to Ramm et al.
U.S. Pat. No. 3,867,272 discloses microelectric devices and circuits, such as those found in semiconductor and hybrid microelectrics. Microelectric devices are rendered unrecognizable and may be destroyed by means of an electrochemical reaction comprising an electro-chemical or chemical etching and/or de-plating process.
U.S. Pat. No. 4,729,970 discloses an electronic device of the type including a thin film body having a superposed electrode and further including short circuit defects therein passivated by conversion process in which the electrical resistivity of the electrode material is increased proximate the defect regions. Conversion is accomplished by exposing the electrode material to a conversion reagent and activating the reagent proximate the defect regions. The process may be utilized for a variety of differently configured devices, and may be readily adapted for use in a roll-to-roll device fabrication process.
U.S. Pat. No. 4,749,454 discloses a method of removing electrical shorts and shunts from a thin-film semiconductor device having pairs of electrodes with exposed contact surfaces wherein each pair of electrodes is separated by a semiconductor film. The disclosed method comprises the steps of coating the exposed contact surfaces with an ionic solution and successively applying a reverse-bias voltage between the exposed contact surfaces of each pair of electrodes. The ionic solution has an etching rate that increases with increased temperature so that the leakage current flowing through shorts and shunts located between each respective pair of electrodes in response to the reverse-bias voltage will create a local temperature increase at the shorts and shunts and selectively etch or oxidize the shorts and shunts, rendering them substantially nonconductive. The exposed contact surfaces can be coated using a sponge application or spray apparatus. The preferred ionic solution comprises an acid mixture diluted to one part in at least five parts water.
U.S. Pat. No. 4,782,028 discloses a method for forming a detector device, such as thinned bulk silicon blocked impurity transducer infrared detector, by thinning a semiconductor substrate and processing the thinned region on two sides to form the detector device. The semiconductor substrate is thinned to form a cavity in the substrate. Further processing on both sides of the thinned region is performed while the thinned region is still connected to the thicker substrate. The thinned region is then separated from the substrate upon completion of the given processing steps. The device may then be mounted to a readout device.
U.S. Pat. No. 4,984,358 discloses integrated circuit dies which, while still in wafer form, are prepared for stacking without requiring packaging. Holes are made through a wafer having a plurality of integrated circuit dies and are placed between the dies and adjacent the die pads. A layer of insulating material is placed on the wafer and in the outer periphery of the holes. An electrically conductive connection is made between the top of each pad and the inside of the insulating material in an adjacent hole. The insulating layer and the electrically conductive layer can be further extended to the backside of the dies if desired. The dies are separated from each other and can be assembled in a stack and/or surface mounted to a substrate.
U.S. Pat. No. 5,202,018 discloses the invention relating to the electrochemical dissolution of semiconductors by alternating applications of anodic and cathodic direct currents to an electrode formed by contacting a semiconductor material with an electrolyte.
U.S. Pat. No. 5,543,585 discloses a simple process for card assembly by direct chip attachment using electrically conductive adhesives. Methods are disclosed which create the same intermediate wafer product with a layer of insulative thermoplastic and conductive thermoplastic bumps. After sawing or dicing the wafer to form the chips, the chips are adhered to chip carriers with conductive pads which match the conductive thermoplastic bumps, using heat and pressure. Chips may be easily removed and replaced using heat.
U.S. Pat. No. 5,591,678 discloses a microelectric device, which is fabricated by furnishing a first substrate having a silicon etchable layer, a silicon dioxide etch-stop layer overlying the silicon layer, and a single-crystal silicon wafer overlying the etch-stop layer. The wafer has a front surface not contacting the etch stop layer. A microelectronic circuit element is formed in the single-crystal silicon wafer. The method further includes attaching the front surface of the single-crystal silicon wafer to a second substrate, and etching away the silicon layer of the first substrate down to the etch-stop layer. The second substrate may also have a microelectronic circuit element therein that can be electrically interconnected to the microelectronic circuit element.
U.S. Pat. No. 5,656,548 discloses a multi-layered structure fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in separate wafer or thin film material and then transferred onto the layered structure and subsequently interconnected.
U.S. Pat. No. 5,656,552 discloses a method of making a multi-chip module by thinning individual integrated circuit die or an integrated circuit wafer containing multiple integrated circuits, bonding thinned dice or a thinned wafer to a mylar, polyimide, semiconductor, or a ceramic substrate, and depositing at least one interconnect material over the wafer, where the first interconnect layer is deposited directly over the wafer. A dielectric layer is disclosed as being deposited over each of the interconnect layers. Vias are opened in the dielectric layers in order to interconnect the dice and multip-chip module as required, and the substrate is removed to form a thin, conformal, and high-yielding multi-chip module.
U.S. Pat. No. 5,716,881 discloses a fabrication process for integrating stacked capacitor DRAM devices, and thin film transistor SRAM devices. The fabrication process includes combing key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices.
U.S. Pat. No. 5,770,487 discloses a method of manufacturing a device whereby a layer structure with semiconductor elements and conductor tracks is formed on a first side of a semiconductor wafer which is provided with a layer of semiconductor material disposed on an insulating layer. The semiconductor wafer is subsequently fastened with the first side to a support wafer by means of a glue layer. The support wafer is provided with a metallization. Material is then removed from the semiconductor wafer from the second side of the semiconductor wafer until the insulating layer is exposed. Contact windows are provided in the insulating layer from the first side of the semiconductor wafer before the latter is refastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer and after the insulating layer has been exposed.
U.S. Pat. No. 5,784,261 discloses formation of low profile microchip module assemblies by first mounting one or more active semiconductor integrated circuit chips on a multilayer metallization and dielectric structure disposed on a substrate by wire bonding or flip-chip solder bonding, and then inverting the substrate and mounting it on a printed circuit board by means of solder bump connections. The solder bump connections are sufficiently high for the chips to be held clear of the printed circuit board.
U.S. Pat. No. 5,807,783 discloses a bonded wafer having a first handle wafer, a device layer, an interconnected layer, and a number of vias filled with conductive material that extends between surfaces of the device layer. The interconnect layer has conductors that connect internal device contacts to the conductive vias. A second handle wafer of glass is bonded to the interconnect layer and the first handle wafer is removed. Bottom, external contacts are formed on a surface of device layer.
U.S. Pat. No. 5,811,879 discloses a multi-chip module (MCM) and method of manufacturing same which provides for attachment of semiconductor dice to both sides of the MCM printed circuit boards (PCB). Semiconductor dice, attached to the top surface of the PCB, may be attached by conventional wire bonding, TAB or flip chip methods. Those semiconductor dice attached to the bottom surface of the PCB are wire bonded or TAB connected to the top surface through openings in the PCB. The openings provide a lead-over chip (LOC) arrangement for those semiconductor dice attached to the bottom surface. The bottom surface of the PCB may be provided with die recesses into which the openings extend, to receive the dice and bring their active surfaces even closer to the top surface of the PCB for wire bonding.
U.S. Pat. No. 5,838,545 discloses a high performance, low cost multi-chip module package using a heatsink as a substrate with thin film wiring techniques or multilayered wiring techniques for interconnection of the chips on the surface of the module and a solder column grid array or solder ball grid array for interconnection to the next level of packaging (printed circuit board). The columns or balls create a space between the board and module with the chips being in the space and provide the required interconnect density.
U.S. Pat. No. 5,843,806 discloses methods for packaging TAB-BGA integrated circuits which include providing a double-sided polyimide, forming first dry film layers, sequentially performing a multi-layer electroplating operation of electro-coppering, electronickelling, gold plating and electronickelling again (or electronickelling and gold plating, or electro-coppering and electronickelling), and removing the first dry film layers. A lower second dry film layer serves as a mask for etching a bottom thin copper layer to define a plurality of predetermined openings, and the bottom thin copper layer serves as a mask for applying a laser etching operation to the polymide substrate to define holes without totally penetrating the polymide substrate. An electrolytic plating operation is applied to the holes for forming protruding contacts, and the exposed top thin copper layer is etched or removed. A chip installation hole and a plurality of through holes are respectively defined by performing a laser drilling operation, and a chip is attached to the two electroplated multi-layer (or double-layer) protrusions beside the chip installation hole by using a single point bond method.
U.S. Pat. No. 5,851,845 discloses a method for packaging semiconductor dice. The package includes a thinned die mounted on a compliant adhesive layer disposed on a substrate. The package is formed by providing a wafer containing a plurality of dice, thinning a backside of the wafer by etching or polishing, attaching the thinned wafer to the substrate, and then dicing the wafer. The semiconductor package may be mounted to a supporting substrate such as a printed circuit board in a chip-on-board configuration. The compliant adhesive layer and substrate of the package eliminate stresses and cracking of the die caused by a thermal mismatch between the die and supporting substrate. In addition, the semiconductor package can be mounted in a flip chip configuration with the substrate for the package protecting a backside of the die from radiation.
U.S. Pat. No. 5,856,937 discloses a processor module having a cache of SRAM chips mounted on both a back and front surface, and de-coupling capacities mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor may be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself.
U.S. Pat. No. 5,859,397 discloses a process for producing a photovoltaic element by the steps of: providing a photovoltaic element comprising a lower electrode layer having a metallic layer comprising aluminum or an aluminum compound and a transparent and electrically conductive layer, a photoelectric conversion semiconductor layer, and a transparent electrode layer stacked on an electrically conductive surface of a substrate, and immersing the photovoltaic element in an electrolyte solution to passivate a short-circuited current path defect present in the photovoltaic element by the action of an electric field.
U.S. Pat. No. 5,863,412 discloses a method for etching an object having a portion to be etched on the surface thereof. The method comprises the steps of: immersing the object in an electrolyte solution such that the object serves as a negative electrode, arranging a counter electrode having a pattern corresponding to a desired etching pattern to be formed at the portion to be etched of the object in the electrolyte solution so as to maintain a predetermined interval between the counter electrode and the object, and applying a direct current or a pulse current between the object and the counter electrode to etch the portion to be etched of the object into a pattern corresponding to the pattern of the counter electrode.
U.S. Pat. No. 5,863,829 discloses a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate onto a semiconductor base wafer to form a bonded wafer. The active substrate is surface-grounded and then spin etched.
U.S. Pat. No. 5,866,441 discloses an electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits and having protuberances on the conductive pattern of the substrate. The protuberances are ductile metal which is capable of being metallurgically bonded to the input/output pads of semiconductor devices. The input/output pads of the semiconductor devices are simulataneously bonded to the protuberances of the packaging module.
U.S. Pat. No. 5,872,025 discloses stacked three-dimensional devices prepared by stacking wafers as an alternative to stacking individual devices. Chip regions are formed on several wafers with each chip region being surrounded by a separation region, such as an insulator filled trench. The wafers are subsequently stacked with the chip regions in alignment. Aligning the wafers may be facilitated using notched regions in the periphery of the wafers. The wafers are subsequently joined together by lamination. After laminating the stacks of wafers, stacks of chips are separated by etching, dicing or other processes, which separate out stacked chip devices from the stacked wafer at the chip separation regions.
U.S. Pat. No. 5,872,700 discloses microcircuit packaging techniques, and more particularly packaging of a structure compiled of several microcircuits. Unpackaged components are mounted on a substrate, and to the substrate there is attached a tape. Solder bumps are formed on a side of the tape so that the whole structure can be mounted to a circuit board by applying conventional surface-mounting techniques. The connections between the solder bumps and the I/O lines of the substrate are realised by conductive patterns formed on the tape, and by leads provided at the edges of the tape.
U.S. Pat. No. 5,877,034 discloses a method of making a three-dimensional integrated circuit by the steps of: transferring fully processed devices from a device layer of first substrate to an auxiliary substrate, separating the auxiliary substrate and the devices thereon into individual chips, testing the chips for their functionality and mounting functioning chips on a carrier substrate in a side-by-side arrangement to form a device layer therein, and thereafter mounting a further device layer on the device layer of the carrier substrate.
Accordingly, there is a need in the art to provide a capacitance to the MCM module substrate which is capable of operating at higher frequencies. More specifically, there is a need for a method for efficiently producing a reliable high-density multilayer circuit structure in a cost effective manner.